谢腰。
首先要明白的一点是：摩尔定律首先是一条经济上的定律，然后才是工程科学方面的定律。
集成电路从设计到生产，其指挥棒都是以盈利为目标的。芯片集成度翻倍，成本减半，在系统集成商的角度就是性能翻倍，器件集成度翻番，价格减半在消费者眼里就是从大哥大到小灵通再到智能手机，越来越物美价廉。芯片的系统集成产品是以PC，手机，平板等等为代表的消费电子。如果从小灵通到现在还是一直都是小灵通，没有其它可替代产品，那小灵通的市场早就饱和了，产能过剩，企业难以为继。实际上，平均每两年就会出一代新芯片，集成度翻倍，成本减半。使得消费电子越来越物美价廉，刺激消费。Intel每两年出一代产品，十年出五代产品，就能赚五倍。在市场上的产品饱和前，下一代产品即使已经研发出来，也要等市场上的产品把玛丽赚干净了，才会投入市场。【这里有个证据，2007年3月，INTEL宣布在大连投资25亿＄建立一个12inch的90nm晶圆工厂，2009年6月，INTEL宣布大连芯片厂将以65nm制造工艺替代90nm工艺，原因是此时国内已经开始了65nm的晶圆制造，so，不是INTEL没有更先进的制程，只是人家在利用旧制程把市场上该吸的血吸干净前，根本没有必要推出新工艺】所以，芯片必然要以每两年(一年半)集成度翻倍，价格减半来迎合市场，太慢了市场已饱和，公司收支不平衡，会引起财务上的问题。太快了，一是这一款芯片没有最大化他的盈利能力，二是在技术上研发跨越不了一代一代之间的积累。在摩尔定律失效后，集成电路产业会成为传统制造业，盈利的驱动力转变为新应用，比如以物联网等等为需求的应用。
芯片从设计到制造，工艺进步使得集成度翻倍，成本减半。一片wafer需要重复几十道工序，才能加工出芯片来，而每一道工序的成本都不小。wafer尺寸的增大，使得一块wafer上的芯片数越来越多，平均到每块芯片上的成本降低。性能翻倍要求每个芯片的集成度更高，这样才能在低功耗的要求下更高频的满足更多功能。因此芯片上的晶体管数集成到上亿，而每一个晶体管的特征尺寸从180/130/90/65/45/22/14/7nm不断减小，其中又提出了SOI FINFET Strained Si 半浮栅等等技术。尺寸的缩小使得量子效应成为晶体管设计的重要考虑背景。新材料和新原理成为摩尔定律的突破口。比如利用单电子自旋状态存储0/1，实现数字计算。对于工艺，最重要的一步是光刻和相应的光刻胶，开发一套光刻设备是很昂贵的，其实整个半导体制造都是很昂贵的，学校旁边（我站在寝室窗户边都能看见）最近三星建了个22nm的新闪存芯片项目，据说光一期就投资了70亿$，总投资300亿$，西安为三星项目付出至少2000亿元，实际付出的还可能更多。
上面这些都知道的差不多了，就大概能回答为什么摩尔定律越来越难以为继。一是从经济角度上，更先进的制程需要超乎想象的投资，公司和投资方很难承担这样的风险，而且做出来的芯片不一定能收回成本，跟别谈利润了。二是技术层面的，先进制程的几大限制——光刻（包括光刻设备，光刻胶等等）、器件物理中的量子效应、互连寄生效应、功耗、延时、封装等等。
所以，摩尔定律是从资本运营到工程再到科学相互渗透的经验定律，没有严格准确的表述。什么时候真正是极限，科学家也不敢肯定。
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以下是2014/3/31新闻中关于台湾半导体之父张忠谋对后摩尔时代看法的报道
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台积电董事长张忠谋认为摩尔定律只剩5~6年的寿命，并建议台湾半导体产业必须掌握系统级封装、低功耗、传感器这三大技术，才能抓住发展机会......
2014台湾半导体产业协会(TSIA)年会于27日登场，台积电(2330)董事长暨TSIA名誉理事长张忠谋(见附图)以「NextBigThing」为题发表演说。张忠谋表示，他认为摩尔定律虽已「苟延残喘」，不过估计还有5~6年的寿命。而关于什么是半导体产业的下一个机会?他则点名是物联网(IoT)相关商机，而台湾半导体产业要掌握这波商机，就要掌握系统级封装、低功耗、感测器等三大技术。
张忠谋指出，这几年半导体产业已经连续好几年都仅有3~5%的微幅成长，不过有几家公司，成长幅度远超过这个数字，比方美国的手机晶片大厂高通(Qualcomm)、台湾的联发科(2454)、以及台积电，这几年都缴出双位数成长、甚至近2成的亮眼成绩。之所以能够如此，就是掌握了智慧型手机、平板等行动装置(mobileproduct)这个「BigThing」。
张忠谋表示，目前每台智慧型手机，对台积的营收贡献达8美元，而给高通带来的营收贡献还高于此，因此行动装置无疑就是此刻的「BigThing」，估计台积今、明两年还能享受行动装置所带来的商机。不过问题在于，下一个「BigThing」是什么?
张忠谋:摩尔定律将死 半导体迎三大机会
他观察，像是GoogleGlass这些穿戴式装置，以及智慧家庭等相关产品，都与物联网有关，物联网这个构想很可能就是下一个「BigThing」。张忠谋指出，物联网产业最赚的公司「不会是半导体公司」，而是能够整合整个系统的公司，像是Amazon、Google、华为、Cisco、中国阿里巴巴这些企业最有崛起的机会。他预估，物联网相关商机可望于未来5~10年间发酵。
惟张忠谋表示，半导体虽不会是物联网趋势中最赚钱的公司，不会是这个「新世界的红人」，不过无论是哪一家公司脱颖而出，都将需要半导体产业的支撑。
他呼吁，台湾半导体产业若要在此波物联网的浪潮中站稳脚跟生存下来，必须掌握三大关键技术方向。第一，就是透过系统级封装技术，让一颗晶片能够整合更多功能，也更省空间。他举例，比方逻辑IC固然需要较先进的制程，不过像RF射频晶片、I/O控制IC等晶片则不需要，半导体厂商可以透过将16奈米、20奈米、28奈米等不同制程(node)将晶片个别封装好，再将采用不同制程的晶片全部封装在一起。
第二大方向，他表示，物联网将用到MEMS、Imagery等不同的感测器(Sensor)，去执行测量温度、侦测环境等功能，因此上述感测器相关技术，也是半导体公司要脱颖而出所必须掌握的技术。
第三，张忠谋表示，物联网的相关产品必须要更加低功耗，甚至功耗还要比智慧型手机低十倍，最好可以一周充一次电。因此低功耗技术，也是半导体公司必须突破的。
他表示，物联网会是一个相当美丽的新世界，不过也存在许多挑战。惟半导体公司若无法克服这些挑战，就会成为低成长、甚至负成长的公司。
很显然，张忠谋的意思是，在后摩尔时代，半导体已成为以市场应用为导向的基础工业。
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下面再附上两篇英文的关于维持摩尔定律前进驱动力的分析，仅供参考
经济篇
What about Moore's Law has made the processor improvement scale so exponentially and predictably?
, PhD, computer science researcher
Votes by
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The answer is simple: economics.
Moore's Law is not caused by technology itself. Technological breakthroughs are unpredictable and if processor improvements were driven by them, then there would be large changes in random time points, with no-change intervals between them.
Processors improvement speed is predictable because it is a result of balance between two forces, which are surprisingly opposite:
To show that these forces are opposite, imagine that you are Intel and you have at your disposal some large number of processor generations, each twice as good as the previous one, and each in unlimited quantity. You can decide when to put each generation on the market. How would you proceed to generate revenue?
When a generation enters the market, two things happen:
Now, the longer you wait with each new generation, the more money you will get from each of them. But in the same time, you yearly revenue would be lower. Your revenue is largest just after releasing next generation. So you need to find a point in which it is no longer reasonable to keep selling old generation and sacrifice it by placing next generation on the market. And this point is defined only by interest rate, not by anything related to technology.
This is of course very simplistic model. In reality Intel at any given point have only several generations at its disposal, and differences between them are not identical. Each next generation must be invented, designed and manufactured, and all of those costs grow with each next generation. Market also grows, but you should include also competitors which affects your calculations. But all those factors do not change the core fact: it is not technology behind the Moore's Law. It is economics. The fact that Moore's Law hold means that technology is constantly ahead of it. And it would be possible to improve processors faster. But it is not economically feasible, so economy stabilizes it into nice predictable exponential growth.
技术篇
What is the main factor facilitating the increase in the number of transistors present in an Integrated Circuits and at the same time decreasing size?
, Former Intel yield engineer, now working with silicon x-ray detectors
Votes by
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It's all about building smaller transistors. With smaller transistors, you can pack more of them close together and therefore get more in a smaller area. To a certain extent, smaller transistors consume less power as well.
There are two aspects -- the technical aspect and the economic aspect.
I'll start with the economic aspect, since that is simpler to explain.
While it is more expensive on a per wafer basis to build smaller transistors, it is significantly less expensive on a per transistor basis and as the technology matures, it is less expensive on a per chip basis as you can cram more chips on a wafer when the transistors involved are smaller, up until the point where it's so much more expensive per wafer that it is no longer cheaper per transistor.
TSMC's processes by cost per transistor. In short, Nvidia isn't happy with TSMC's 20nm process.
Credit:
Another factor in scaling down is power consumption. Since we have so many mobile devices and there's keen demand on battery life, many consumers are willing to pay a little more for a lower power device, and there is a big scaling aspect to power consumption.
As for the technical aspects, that's a bit more challenging to answer. There are a number of factors that make scaling transistors down more difficult.
The first and most obvious one is
-- the process for putting down patterns on the wafer for defining geometric features. There are multiple methods for how to make those smaller. For a while, the critical aspect was getting the
down by using shorter wavelengths.
When that hit a dead stop at about 60nm, the industry got more creative and ended up using
techniques to make features smaller.
only one of many ways to do it.
The next big push on making smaller lithography patterns is
, using wavelengths around 13.5nm. Building EUV lasers is not an easy or cheap thing to do, and there are still issues with power output and therefore throughput.
The other biggest aspect on scaling down transistors is static power consumption, or leakage current.
Credit:
In order to reduce the power at smaller process nodes, you have to get static power consumption down, and the way to do that is to change the way the transistors work. There have been numerous improvements to that, which I list in
Strained silicon:
Hi-k dielectrics
And most recently, the use of FinFETs
Summary:
Main factor is that overall smaller process technology nodes are cheaper per transistor and cheaper per chip. That is what motivates process improvement. A secondary economic motivator is a possible money/demand premium on lower power chips.
Main two technical factors are photolithography (how to actually make smaller physical features) and whatever they do to push leakage current down.
